1. Field of the Invention
The present invention relates generally to electronic circuits and, more particularly, to a nested pair of phase-locked loop (PLL) circuits that are agile, in that multiple frequencies can be synthesized at the output, a low phase noise surface acoustic wave (SAW) resonator is used to synchronize the output and, with one of the PLL circuits being a low bandwidth PLL, jitter on the output is attenuated.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In electronic circuits, clock distribution occurs throughout the circuit to synchronize performance of the product. Clock skew and jitter can occur if poor clock distribution is present. This may cause problems in operation of the electronic circuit. Techniques have been developed using PLL's to successfully manage these problems and reduce both to an acceptable level. However, the current solutions are not without some disadvantages.
A PLL can be used for clock distribution, clock multiplication, skew suppression, clock recovery, and other applications. A PLL can suppress skew and jitter in digital systems (for example, clock to data out delay), and can generate multiple phases of output clocks. In an exemplary application, a PLL may operate as a clock multiplier, where an input clock of 10 MHz may be multiplied by the PLL to yield, for example, 1000 MHz. Typically, a PLL includes a phase frequency detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase frequency detector detects and tracks small differences in phase and frequency between the incoming signal and the output from the VCO, and provides output pulses that are proportional to that difference. In many instances, a PLL can include a frequency divider within the feedback loop between the VCO and the phase frequency detector. For example, an N divider allows the frequency output from the VCO to equal N times the input signal frequency, namely FOUT=N*FIN. In the ideal embodiment, clock multiplication function can result in an output clock that is in perfect phase alignment with the input clock, yet at a higher frequency (i.e., a frequency N times the input frequency).
Therefore, a PLL is oftentimes used as a clock synthesizer. In a 10 GHz XFP optical module, it may be necessary to translate one data/clock rate to another data/clock rate while keeping phase noise as small as possible on that output. The transfer can occur through clock multiplication and, possibly, clock division to achieve a particular ratio between an input and output frequency (FIN and FOUT).
One mechanism in which to generate the output frequency with low phase noise is to utilize a SAW oscillator. As described in “Integrated RF transmitter based on SAW Oscillator,” 23rd EP Solid-State Circuits Conference, September 1997 (herein incorporated by reference), SAW oscillators operate using a SAW resonator coupled to an output amplifier. The resonating frequency can be modified through an input voltage to form what is known as a voltage-controlled SAW oscillator, or VCSO. Further details of a VCSO are set forth in U.S. Pat. No. 6,933,794 (herein incorporated by reference).
A VCSO can be placed in a PLL by substituting a VSCO for the VCO. A primary benefit of a VCSO is that there is very little phase noise at the PLL output. This is due primarily to the VCSO having a high Q factor exceeding, for example, 10,000. Moreover, operation at the fundamental frequency of the resonator avoids any spurious emission on that output. Unfortunately, however, a VCSO has a very narrow pulling range. In other words, the VCSO, while having low phase noise and good jitter attenuation within a PLL, cannot be tuned much beyond 300 ppm.
Recognizing the shortcomings of a VCSO, some PLL circuits use the more traditional inductor/capacitor VCO, or LCVCO. An LCVCO, while having a higher phase noise and greater spurious emissions than a VCSO, can be tuned far beyond the 300 ppm of a VCSO. In some examples, an LCVCO can achieve a tuning range greater than 10%. The synthesized multiple rates associated with, for example, clock recovery in a 10 GHz XFP application, VCSO cannot be utilized because its incoming frequency variation can extend beyond the tuning range of the VCSO.
It would be desirable to implement a clock recovery or translation circuit that has low phase noise with good jitter attenuation of a VCSO within a PLL, yet with a wider range of tunability which conventional VCSO PLL circuits cannot achieve. Thus, a more agile, lower phase noise, clock synthesizer with jitter attenuation is desired.